1. Field of the Invention
The present invention relates to a NAND flash memory using a programming scheme in which programming is conducted successively from a memory cell transistor on the source side.
2. Background Art
When boosting a channel in a memory cell transistor inhibited in programming in a NAND memory cell unit, the channel is more boosted if threshold voltages of memory cell transistors connecting to unselected word lines are in the erase state, especially in a deep erase state.
For example, the EASB programming scheme is proposed as a channel voltage control scheme at the time when programming is inhibited (see, for example, Japanese Patent Laid-Open No. 10-283788). For example, the REASB programming scheme is proposed as another example (see, for example, Japanese Patent Laid-Open No. 2007-87513).
In the EASB programming scheme and the REASB write scheme, sequential programming in which programming is conducted in order from a memory cell transistor on the source line side is premised.
In write operation according to the EASB programming scheme and the REASB programming scheme, a low voltage (for example, 0 V) is supplied to a word line of a memory cell transistor adjacent to the source side of the selected memory cell transistor or located on the source line side to cut it off.
And a write voltage Vpgm is applied to the word line of the selected memory cell transistor, and an intermediate voltage Vpass is applied to unselected word lines other than the word line of the selected memory cell transistor.
In this case, the boosted region is restricted to the selected memory cell transistor and memory cell transistors located on the bit line side as compared with the selected memory cell transistor. And all of these memory cell transistors in the boosted region are brought into the erase state by the sequential programming already described, and a high channel voltage is obtained.
It is attempted to prevent false programming into the memory cell transistor inhibited in programming, by using the EASB and REASB write schemes.